Moore's Law made a simple prediction back in 1965: the number of transistors on a dense integrated circuit would roughly double every two years. Gordon Moore's observation held up well enough, for long enough, that it became a planning assumption for the entire semiconductor industry. Engineers built product roadmaps around it. Software developers assumed the extra headroom would show up on schedule.
That steady doubling has been losing momentum for years now, and the reasons are physical as much as economic. Cramming more transistors into less space eventually runs into problems with heat, power leakage, and the sheer cost of the equipment needed to pattern features at these scales. Foundries like TSMC and Samsung are pushing forward anyway, moving from FinFET transistors to gate-all-around (GAA) nanosheet designs that wrap the gate fully around the channel for better control at smaller sizes. Intel is doing something similar with its 18A process, part of what it calls the “Angstrom Era.” These are real advances, but they cost more per transistor than the old scaling curve did, and the pace has slowed from Moore's original two-year cadence.
None of that means progress has stopped. It means the industry has stopped relying on one trick to keep computing power climbing and started stacking several. Reconfigurable logic, 3D packaging, chiplet-based designs, and two genuinely different computing paradigms, quantum and photonic, are all doing part of the work that shrinking transistors used to do alone.
Most chips are hardwired for one job. A field-programmable gate array (FPGA) is built differently: it's an integrated circuit engineers can reconfigure after it ships, rewiring its internal logic gates to suit a new task instead of ordering a new chip. The idea isn't new. Steve Casselman filed a patent for a reprogrammable FPGA architecture with roughly 600,000 gates back in 1992, and the technology has been a staple of industrial, telecom, and automotive electronics ever since.
What's changed is where FPGAs sit in the broader chip market. AMD's Xilinx division and Intel's Altera business, now operating independently again after Silver Lake took a majority stake in 2025, still dominate the space, but the growth is coming from AI. FPGAs are increasingly used as pre-processing and networking accelerators sitting alongside GPUs in data centers, handling tasks like data formatting, encryption, and traffic management in hardware so the GPU can stay focused on the model itself. AMD's Versal adaptive SoCs and Altera's Agilex line are both built around that role. Because an FPGA can be reprogrammed as workloads and standards change, it remains a practical hedge for engineers who need custom logic without committing to a full custom ASIC.
Instead of spreading a design across a single flat die, 3D integration stacks multiple silicon layers vertically and links them with through-silicon vias (TSVs), tiny vertical wires that let the stacked dies function as one chip. This isn't a lab curiosity anymore. High-bandwidth memory (HBM) used across the AI accelerator market is built this way, and AMD's 3D V-Cache, which stacks extra cache memory directly on top of a processor die, has shipped in consumer and server chips for several product generations now.
The appeal is straightforward. Keeping signals inside a single package instead of routing them across a board cuts the distance data has to travel, which lowers power draw and increases bandwidth at the same time. It also packs more function into a smaller footprint, which matters for anything space- or weight-constrained. The tradeoff is thermal: stacking active silicon on top of more active silicon concentrates heat in a smaller volume, which is one reason packaging and cooling design have become as important to performance roadmaps as the transistors themselves.
The multi-chip module (MCM) approach, building a chip out of several smaller dies assembled in one package rather than a single large monolithic die, has gone from a workaround to the default strategy for high-performance silicon. The industry mostly calls this chiplet design now. AMD has used it in its EPYC and Ryzen lines for years, pairing a central I/O die with separate compute chiplets. Intel does similar work through its Foveros and EMIB packaging technologies. The draw is yield and cost: smaller dies fail less often in manufacturing than one giant die does, and a design can mix chiplets built on different process nodes, buying older, cheaper nodes for parts of the circuit that don't need the newest transistors.
The main friction has been getting chiplets from different vendors to talk to each other reliably. That's what the Universal Chiplet Interconnect Express (UCIe) standard, backed by Intel, AMD, and most of the rest of the industry, is meant to solve, though proprietary interconnects like Infinity Fabric and EMIB are still doing a lot of the heavy lifting in practice. For engineers sourcing or specifying hardware around these chips, the packaging and interconnect choice increasingly matters as much as the silicon inside.
Quantum computing has moved from a research curiosity to something with real, if narrow, hardware milestones. Google's Willow processor demonstrated error correction below the threshold where adding more physical qubits actually reduces the overall error rate, a result the field had been chasing for years. IBM's newer Nighthawk processor and its Loon architecture are aimed at the same problem from a different angle, and IBM has said it's targeting a demonstration of quantum advantage on a commercially relevant problem by the end of 2026, with fault-tolerant systems projected for 2029.
None of this means quantum hardware is ready to run a factory floor's production scheduling or a supply chain optimization problem today. The realistic read from people working in the field is that quantum computing is worth watching and piloting, not something to build a business-critical process around in the near term. But the trajectory is faster than it was even three years ago, and quantum bits, unlike transistors, aren't trying to solve the same problem Moore's Law was built around. They're a different kind of scaling entirely.
Optical or photonic computing uses light instead of electrical current to move and, increasingly, to process data. The clearest near-term win is inside data centers, where co-packaged optics are replacing copper interconnects between racks of AI accelerators. Nvidia's upcoming Quantum-X and Spectrum-X networking platforms are built around this idea, and the reasoning is simple: electrical signals lose energy and generate heat over distance, while light doesn't have the same resistive losses.
Photonic compute, actually doing logic and math with light rather than just moving data with it, is earlier stage but no longer theoretical. Companies like Lightmatter and Q.ANT have shipped or announced photonic processors aimed at AI inference workloads, built on thin-film lithium niobate and silicon photonics platforms. The pitch is lower energy use per calculation than a conventional digital chip, since photonic components don't generate the same resistive heat that transistors do. Full photonic computing, replacing conventional processors wholesale, is still years away. Photonic interconnects replacing copper inside AI infrastructure is happening now.
None of these architectures are replacing conventional silicon outright. They're each solving a piece of the problem that shrinking transistors used to solve on its own: more logic per package, less power per operation, faster signal paths, and in the case of quantum and photonic computing, entirely different ways of framing the calculation itself. For engineers designing enclosures, thermal solutions, and mounting hardware around this new generation of denser, hotter-running, more tightly packaged electronics, the physical design constraints keep tightening even as the chips themselves get more capable.
